1. Field of Invention
The present invention generally relates to the memory device, and more particularly to the word line decoder circuit of the memory device.
2. Description of Prior Art
The memory device has a plurality of memory cells. When there are a plurality of data being to be stored (or read), the memory device must receive the word line selected signal of each of the data, so as to store the plurality of the data in the corresponding memory cells (or read the plurality of the data from the corresponding memory cells) according to the word line selected signals. Accordingly, the word line driver circuit is adapted in the memory device to generate the word line selected signals.
Referring to FIG. 1, FIG. 1 is a circuit diagram showing a conventional word line decoder circuit 10 provided by Intel Corporation. The conventional word line decoder circuit 10 comprises a controllable pull-down circuit 11, eight local decoders 12_1˜12_8, a PMOS transistor P4, and eight word line clusters 13_1˜13_8. Wherein each of the word line clusters 13_1˜13_8 comprises sixteen row drivers 14_1˜14_16. Each of the local decoders 12_1˜12_8 comprises a NMOS transistor N1 and two PMOS transistors P1, P2. The controllable pull-down circuit 11 comprises two NMOS transistors N2 and N3. Each of the row drivers 14_1˜14_16 comprises a PMOS transistor P3 and two NMOS transistors N4, N5. The connections of all elements of the sector 10 of the conventional word line decoder circuit can be seen in FIG. 1, and are not be described herein.
Referring to FIG. 2, FIG. 2 is a circuit diagram showing the conventional word line decoder circuit 10 provided by Intel Corporation, when a word line WL<1> is selected. Now the conventional word line decoder circuit 10 is selected, and sector select signals BLKSEL and BLKSELHB are VCC and 0 respectively. The word line WL<1> is selected, and thus a local pre-decoding signal PREA<1> and a row driver select signal PRERN<L> are VCC and 0 respectively. Other local pre-decoding signals PREA<2>˜PREA<7> are 0, other row driver select signals PRERN<2>˜PRERN<16> are VPX, and a pre-decoding signal PREB<1> and a bias signal AWLH are 0 and VBIAS respectively. When operating in READ mode, power supplies VPIXH and VPXH are VPX, and a power supply VNX is 0.
The PMOS transistor P4 is turned on, and the node VPXX is VPX. The PMOS transistor P1 of the local decoder 12_1 and the NMOS transistor N1 of the local decoder 12_1 are turned on, and the NMOS transistors N2, N3 of the controllable pull-down circuit 11 are turned on. Thus a reset signal VGRST<1> is 0. Therefore, the PMOS transistor P2 of the local decoder 12_1 is turned on, and in the word line cluster 13_1, the NMOS transistors N5 of the row drivers 14_1˜14_16 are turned off. The node VX<1> is VPX. The row driver select signal PRERN<1> is 0, and thus, in the word line cluster 13_1, the PMOS transistor P3 of the row driver 14_1 is turned on, and the NMOS transistor N4 of the row driver 14_1 is turned off. Therefore, the word line WL<1> is VPX. On the contrary, the other row driver select signals PRERN<2>˜PRERN<16> are VPX. In the word line cluster 13_1, the PMOS transistors P3 of the row drivers 14_2˜14_16 are turned off, and the NMOS transistors N4 of the row drivers 14_2˜14_16 are turned on. Therefore, the word lines WL<2>˜WL<16> is 0.
The PMOS transistors P1 of the local decoders 12_2˜12_8 are turned on, and the NMOS transistors N1 of the local decoders 12_2˜12_8 are turned off. Therefore reset signals VGRST<2>˜VGRST<8> are VPX, and the PMOS transistors P2 of the local decoders 12_2˜12_8 are turned off. The node VX<8> is high impendence. In the word line clusters 13_2˜13_8, the NMOS transistors N5 of the row drivers 14_1˜14_16 are turned on. The row driver select signal PRERN<1> is 0, and thus, in the word line clusters 13_2˜13_8, the PMOS transistor P3 of the row drivers 14_1 is turned off, and the NMOS transistor N4 of the row driver 14_1 is turned off. Therefore, the word line WL<1> is 0. On the contrary, the other row driver select signals PRERN<2>˜PRERN<16> are VPX. In the word line clusters 13_2˜13_7, the PMOS transistors P3 of the row drivers 14_2˜14_16 are turned off, and the NMOS transistors N4 of the row drivers 14_2˜14_16 are turned on. Therefore, the word lines WL<2>˜WL<16> is 0.
A size of each of the PMOS transistors P1 may be a design issue. Taking FIG. 2 as an example, when the sizes of the PMOS transistors P1 are small, the reset signal VGRST<1> is pulled down to 0 fast, the node VX<1> is pulled up to VPX fast, and the NMOS transistors N5 in the word line cluster 13_1 are turned off fast. Therefore, the selected word line WL<1> is pulled up to VPX fast. However, the reset signals VGRST<2>˜VGRST<8> are pulled up to VPX slowly, and the NMOS transistors N5 in the word line clusters 13_2˜13_8 are turned on slowly. Therefore, the non-selected word lines WL<17>˜WL<128> are pulled down to 0 slowly.
On the contrary, when the sizes of the PMOS transistors P1 are large, the reset signals VGRST<2>˜VGRST<8> are pulled up to VPX fast, and the NMOS transistors N5 in the word line clusters 13_2˜13_8 are turned on fast. Therefore, the non-selected word lines WL<17>˜WL<128> are pulled down to 0 fast. However, the reset signal VGRST<1> is pulled down to 0 slowly, and the NMOS transistors N5 in the word line cluster 13_1 are turned off slowly. If the reset signal VGRST<1> is too large, the NMOS transistors N5 of the row driver 14_1 in the word line cluster 13_1 might be turned on. Therefore, the selected word line WL<1> is pulled up to VPX slowly, or even not reached to VPX.
In summary, the sizes of the PMOS transistors P1 must fall in an appropriate range, so as to avoid slow read speeds for the non-selected and selected word lines.
Furthermore, still taking FIG. 2 as an example, except the PMOS transistor P3 and the NMOS transistor N4 of the row driver 14_1 in the word line cluster 13_1, all of the PMOS transistors P3 and the NMOS transistors N4 are charged to VPX. The NMOS transistors N4 of the word line clusters 13_2˜13_8 are charged to VPX, too. In the real world, the voltage VPX is generated by an internal pump circuit. The power efficiency of the internal pump circuit is about 20%˜30%, and hence having large power consumptions and a large setting time for setting VPX. Therefore a problem of a read speed for the selected word line occurs.
Accordingly, the conventional word line decoder circuit may have a problem of the read speeds for the selected or the non-selected word line, and a problem power of large power consumptions.